According to Samsung Foundry, the world’s second largest independent foundry after TSMC, some changes have been made to its 3nm process node. Anand Tech Samsung Foundry’s first chips manufactured using 3nm process, 3GE (3nm gate all around early), will reportedly go into high volume manufacturing a year later than usual. It was also removed from Samsung’s roadmap, indicating that 3GEE could only be developed for indoor use.
“Regarding the 3GAE process, we are in talks with consumers and expect to make 3GAE mass-produced in 2022,” said a Samsung spokesperson. The successor to 3GE, the 3GAP (3NM Gate All Around Plus) node is still on the roadmap, with volume manufacturing expected to begin in 2023. The above roadmap was opened in 2021 at the Foundry Forum in China. Samsung Foundry introduced its latest roadmap, which was later republished on Baidu and Weibo.
As far as chips using its older FinFET transistor architecture are concerned, Samsung has added 5LPP, and 4LPP to its roadmap in 2021 and 2022, respectively, with high-volume manufacturing sets. When Samsung unveiled its 3GE and 3GAP nodes in May 2019, announcing that it will announce a 35% increase in performance, up from 50% in power consumption compared to 7LPP. Deficiency that is currently the process node of the previous generation.
Samsung Foundry’s Roadmap 322E does not show high volume output for the process node for 2022. Probably most indicate that it will be used for indoor components.
At the same time, in 2019, it was announced that volume production using 3GAA (Gate-All-Around Transistor Architecture) would begin in late 2021. With the new launch date of 2022 for the initial process around 3nm gate-all, no one can conclude that there has been a slight delay by Samsung or on the wrong calculation. Either way, this is not considered a big deal because the early nodes of Semi are not used extensively by the manufacturers.
Just a few days ago, Samsung Foundry tapped a 3nm chip that uses its Get-All-Around (GAA) transistor architecture. Tapping the chip is the last step in its design cycle, which leads to one of two conclusions: the chip design works or it doesn’t. In the latter case, minor repairs may be required or a complete restoration of the design may be required.